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    • 专利摘要:
    A focal plane array is provided which includes an array of photodetectors, each photodetector being in electrical communication with a corresponding one of an electrode of an output integrated circuit. The photodetector array includes an insulating layer, a blocking layer including at least one blind via hole, and an active layer formed between the insulating layer and the blocking layer. A first portion of the blocking layer transmits radiation having a first wavelength and reflects radiation having a second wavelength which is less than the first wavelength. A diameter of the at least one blind via hole is chosen to allow radiation of the second wavelength to pass through the at least one blind via hole. Fig. 1B
    公开号:BE1022761B1
    申请号:E2014/0362
    申请日:2014-05-19
    公开日:2016-08-30
    发明作者:Peter E. Dixon
    申请人:Sensors Unlimited, Inc.；
    IPC主号:
    专利说明:

    PERFORATED LOCKING LAYER FOR IMPROVED BROADBAND ANSWERING IN A FOCAL PLAN NETWORK
    Field of the Invention The invention generally relates to the field of photocetectors, particularly near infrared (NIR) and short wave infrared (SWIR) photodetectors, and specifically, the field of focal plane arrays comprising a plurality of photodetectors.
    History of the invention
    The visible spectrum of light extends to wavelengths of about. 0.4 micrometer to about 0.7 micrometer. The ounce lengths larger than the visible wavelengths can be detected by dedicated sensors. However, SWIR light is a reflective light that bounces on objects in a manner similar to visible light. As a result of its reflective nature, the detected SWIR light may have shadows and contrast in its imagery. For low light level imaging applications, the noise / leakage current, such as the dark current, must be reduced to obtain sufficient sensitivity.
    Sensors designed from materials such as mercury and cadmium teliuride (HgCdTe) or indium antimonide {InSb) can be very sensitive in the SWIR to MWIR band. However, at least in the case of HgCdTe, due to the high dark current due to the narrow bandgap, these devices must be mechanically cooled, often at cryogenic temperatures, which increases energy consumption, size and the cost of cameras that use these sensors. More recent methods allow MWIR [1.1 p to 3.5 pra] SWIR imaging at higher operating temperatures, but the SWa (size, weight and power) remain a challenge, and similarly, MWIR systems can not process visible energy, so systems requiring a visible signal response (typically blue at 450 nm to red at 700 nm) should also employ EO sensors for visible imaging and then merge the two data streams with merge algorithms or provide dual displays to handle the two separate bands. Thermal imaging systems are another class of camera with good detection capabilities. If thermal imaging can detect the presence of a hot object against a cold background, they offer a low resolution and a dynamic range across ur. spectral content requiring the capture of reflected light, including the observation of objects such as ur. building, ur. furniture or other materials that provide minimal thermal deviation from the background scene. In addition, because of these material properties of many glasses, especially those used in industrial environments, the LWIR (thermal spectrum typically from 8 pm to 12 pm) is not transmitted, but absorbed or reflected in the medium, although that thermal sensing alone is not capable of imaging through common window materials such as ANSI standard buildings or shielding in industrial assembly lines requiring these measurements.
    In addition, CMOS and CCD imaging systems are excellent devices that continue to evolve to meet military needs. But these sensors are typically used for a visible light response, having a near infrared response at the short end of the IR spectrum (typically intersecting at no more than 11C0 nm). To image well for night vision applications, silicon-based imaging systems require significant amplification, which creates image quality challenges due to noise amplification. Otherwise, silicon-based imaging systems have an indirect band gap and, if they can be manufactured at low cost, with high resolution, they suffer from a relatively low sensitivity to N IR energy compared to materials. III-V direct bandgap with a narrow absorption band to achieve higher sensitivity on the full SWIR band, including indium gallium arsenide.
    InGaAs sensors can be made extremely sensitive (D * -1E + 14 Jones in commercial InGaAs imaging systems) by literally counting individual photons. Subsequently, when constructed in the form of focal plane arrays with thousands or millions of tiny point sensors or photodiode sensor pixels, the SWIR cameras will work in very dark conditions. Images from an InGaAs camera can be comparable to visible images in terms of resolution and detail; however, SWIR images are not in color. This makes the objects easily recognizable and offers one of the tactical advantages of SWIR, namely, the identification of objects or individuals.
    For conventional backlit photodetectors, especially those that are used in hybrid IR focal plane gratings, a backlit imaging plane includes a substrate material with a larger band gap than the active material. InGaAs for the photodetection of SWIR is traditionally grown on indium phosphide (InP) substrates and is capable of providing a photo response in both visible to SWIR (450 nm to 1700) bands. nm). The InP substrate (1.35 eV) has a larger band gap than the lattice-adjusted (0.7 μI) Ir.GaAs, which will limit the useful application of imaging systems. InGaAs at a photo response of 1100 nm - 1700 nm unless the InP substrate is removed. The substrate then acts as a long-pass filter for all the energy that is above its forbidden band. The wavelength is inversely proportional to the energy (E = hc / A, where E is the energy, h is the Planck constant, c is the speed of light, λ is the wavelength), so that a longer wavelength will pass above the absorption "cutoff" of a given material. However, it is desirable to extend the photo response of traditional SWIR composite semiconductor imaging to include shorter (visible) ende lengths, particularly for applications where an IR wave solution short can move the imaging devices having a real visible response incorporated into them.
    In an approach for obtaining a visible response in conventional InGaAs / InP based imaging systems, for example, the substrate is removed using mechanical polishing methods or using etch stop layers. However, because the substrate of these systems is commonly used as the cathode of the diode array (substrate contact), the substrate can not be completely eliminated. These solutions are currently available commercially and as special applications.
    In some material systems, as discussed in the discussion above, the substrate layer or buffer layer has a larger bandgap than the lower bandgap semiconductor active layer. In these systems, the lower bandgap semiconductors suffer from a high recombination rate if pn junctions are exposed at the surface due to defects, surface conditions and what is commonly referred to as trapping. of carriers. Faulty states reduce the band gap by providing a reduced energy potential for conduction. As a result, the absence of a large bandgap buffer layer (also known as a plating layer) degrades the performance of the device. In fact, the absence of an energy band shifted in a region with a low electric field does not allow efficient migration of photo-generated carriers (minority carriers). As a result, in the absence of a plating layer, the quantum efficiency suffers due to trapping of minority carriers.
    As a result, conventional devices have relied on a careful balance of the thickness of the "blocking layer" (buffer / plating layer) of remaining substrate to achieve desirable electrical properties such as limiting surface reconbinization. while also providing adequate light transmission to the active layer. An approach to minimize surface reconbinization in larger bandgap materials has been to N + doping veneer layers to promote minority carrier migration. In such an approach, as the Fermi level is moved closer to the conduction band of this layer, the result is a migration of carriers that move away from the surface toward the junction. This explains the quantum mechanical dependence on the outermost (exposed) layers of a semiconductor structure. Although it is not limited to a particular theory, it applies as much to the engraved sidewalls as to the "front and back" surfaces of the wafer. As a result, it has become increasingly desirable to leave a layer thick enough to maintain robust control over their electrical performance and the quantum efficiency of the device. However, the optical absorption of the substrate layer requires it to be substantially thin shaped so as to allow the transmission of light of visible wavelength to the active layer. For example, a typical thickness of the blocking layer to obtain an adequate visible response in SWIR imaging systems is less than 1.5 μm.
    However, these thicknesses are vulnerable to pitting and various defects. For robust electrical and mechanical performance, it is desirable to leave this layer as thick as possible without cutting off the photo response for the desired application.
    A disadvantage of a conventional focal plane array, as shown in Figs. 1A-1B, in electrical communication with an integrated output circuit 9 relates to its optical properties. For example, as shown, the photodetector array comprises a continuous support layer 11 which transmits only radiation 22 having a first wavelength, such as infrared (IR) radiation, cost by completely blocking the radiation having a second length of corn, such as visible radiation (screw). It would be desirable to have a focal plane array that overcomes these optical problems.
    It is also important to note that some material systems do not have etch stop layers suitable for performing a method as described above. For example, during manufacture of a conventional Ir.GaAs sensor, selective etch stop layers are grown to allow removal of the overall substrate, including removal of the InP substrate. As such, the methods used for these materials without chemical means to stop the removal of the substrate must use CK P or mechanical lathe or diamond-tipped lathe operations. The thickness control of these methods is very good, but obtaining a thickness less than 2 μm of the remaining "blocking layer" is not practical. The ability to leave the "blocking layer" thicker would improve the manufacturing capacity of these structures. _ Summary
    One embodiment is directed to a focal plane array that includes an array of photodetectors, each photodetector being in electrical communication with a corresponding one of an electrode of an output-integrated circuit. The photodetector array may comprise an insulating layer, a blocking layer comprising at least one blind interconnection hole and an active layer formed between the insulating layer and the blocking layer. A first portion of the blocking layer transmits radiation having a first wavelength and reflects radiation having a second wavelength that is less than the first wavelength. A diameter of at least one blind via is chosen to allow radiation of the second wavelength to pass through the at least one blind via.
    In another embodiment, there is a photodetector. The photodetector may include an insulating layer, a blocking layer that includes at least one blind interconnection hole, an active layer formed between the insulating layer and the blocking layer. A first portion of the blocking layer may transmit radiation having a first wavelength and may reflect radiation having a second wavelength that is less than the first wavelength. A diameter of the at least one blind via hole may be selected to allow radiation of the second wavelength to pass through the at least one blind via.
    Another embodiment is directed to a method of forming a focal plane array. The method may include forming a photodetector array. The photodetector array may include an insulating layer, a blocking layer that includes a first portion that transmits radiation having a first wavelength, and reflects radiation having a second wavelength that is less than the first length of the radiation. wave, and an active layer formed between the insulating layer and the blocking layer. The method may include the electrical connection of the photodetector array to an integrated circuit that output. Each of the photodetectors may be placed in electrical communication with a corresponding one of an electrode of the output integrated circuit. The method may also include forming at least one blind via in the blocking layer of the photodetector array. A diameter of the at least one blind via hole may be selected to allow radiation of the second wavelength to pass through the at least one blind via.
    Advantages of at least one embodiment include an improved visible response for SWIR imaging products. An advantage of at least one embodiment includes an improved visible response to simple thinning of the blocking layer by adding blind vias.
    Additional advantages of the embodiments will become apparent in part from the description which follows and will be partly understood by reading the description or may be learned by the practice of the invention. The advantages will be realized and attained by means of the elements and combinations which are particularly emphasized in the appended claims.
    It is understood that both the above general description and the following detailed description are given by way of example and explanation and in no way limit the invention which is as claimed.
    The accompanying drawings, which are incorporated in and form part of the specification, illustrate forms of. embodiment of the invention and will be used, together with the description, to explain the principles of the invention.
    Brief description of the drawings
    Fig. IA illustrates a top view of a focal plane array.
    Fig. IB illustrates a cross-sectional view of the focal plane array of FIG. IA.
    Fig. 2A illustrates a perspective view of a focal plane array of an embodiment.
    Fig. 2B illustrates a top view of the detector of FIG. 2A.
    Fig. 2C illustrates a cross-sectional view of the detector of FIG. 2A.
    Figs. 3A-3D illustrate manufacturing steps in a method of manufacturing a photodetector according to one embodiment.
    Figs. 4A to 4E illustrate manufacturing steps in a method of manufacturing a focal plane array according to one embodiment.
    Fig. 5 illustrates an embodiment of a focal plane array in operation. Description of the embodiments
    As used herein, the term "blocking layer" may refer to a surface layer, such as a back surface layer, of a photodiode that receives radiation that is directed to the photodiode. . Embodiments described herein include arrays of photodetectors that have been processed with a patterned etching of the substrate or a buffer (blocking) layer remaining, which is the main layer in the optical path of the incoming photon flux. Now, reference will now be made in detail to the present embodiments, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference notations will be used throughout the drawings to refer to the same parts or similar parts.
    If the numerical ranges and parameters establishing the broad object of the invention are approximations, the numerical values mentioned in the specific examples are reported as accurately as possible. However, any numerical value inherently contains some errors necessarily resulting from the standard deviation found in their respective test measurements. In addition, all the ranges described here are meant to encompass all the sub-ranges that are embedded therein. For example, a range of "less than 10" can include all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, all sub-ranges having a minimum value equal to or greater than zero and a maximum value equal to less than 10, for example 1 to 5. In some cases, the numerical values as mentioned for the parameter may assume negative values. In this case, the value given as an example of the range mentioned as "less than 10" may assume negative values, for example, -1, -2, -3, -10, -2C, -30 etc.
    The following embodiments are described for illustrative purposes only with reference to the figures. Those skilled in the art will appreciate that the following description is illustrative in nature and that various variations to the parameters mentioned herein could be made without departing from the scope of the present invention. The specification and examples are meant to be considered as examples only. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments.
    The embodiments described herein, including the focal plane array, as shown in Figs. 2A-2C provide a focal plane array which comprises an array of photodetectors, such as an array of pixel photodiode photodetectors 8 formed on a perforated carrier layer 12, in electrical communication with an output integrated circuit 9. The perforated support layers comprise a support layer which has been modified with at least one blind via, in particular a network of blind vias 13 (i.e., holes in the blocking layer "). The perforated carrier layer may be shaped thin enough to transmit radiation having a first length of wave 22, such as IR radiation, through the carrier layer itself. The blind vias 13 may each be formed with a diameter sufficient to permit transmission of radiation having a second wavelength which is less than that of the first radiation 22, including visible light, through the blind vias, but may be small enough not to disturb the electric field from the surrounding N + material. As a result, the quantum efficiency of a device can not suffer from surface trapping due to the applied field, and the photon transmission can be enhanced due to the absence of the blocking layer.
    As shown in Figs. 3A to 3D, each of the photodiode photodetectors comprising a single pixel may be formed from a wafer 1. The wafer may comprise an insulating / dielectric layer 4, such as a plurality of insulating / dielectric layers, a layer of substrate / -support 3 and an active layer 2 formed between the insulating layer and the blocking layer.
    The wafer may be formed of a composite semiconductor, especially using a substrate crystal and growing additional layers by organometallic vapor phase epitaxy (OMVPE), also known as organometallic chemical vapor deposition. In one embodiment, a photodetector may use, but is not limited to, an InGaAsP material system As such, the substrate may be an indium phsphide (InP) substrate and the layers Epitaxial compositions of various compositions using the InP, InGaAs, InAsP, or quaternary InGaAsP binary materials may be grown on the substrate to form at least one active layer 2. In other embodiments, the imaging devices may comprise photodetectors formed by growing similar support layer structures using substrates made from GaSb, InAs, InSb, GaAs Suitable epitaxial layers for these substrates are disclosed in the art through MOCVD crystal growth firms or other engineers specialized in epitaxial growth or in the design and manufacture of composite semiconductor devices. The material system for a given substrate can be determined by designing the composition of organic compounds such that the lattice constant is appropriate to achieve the desired electro-optical performance.
    For IR imaging applications, the typical electrical specification for these materials is such that the substrate is sulfur-doped N + type inP and the added active, buffer and plating layers are not intentionally doped (NID) or be slightly of type N (N-) or strongly of type N (N +). A typical JMOCVD epitaxial growth type N doping is obtained using silicon to provide an additional electron to the group III element on the network. As a result, the composite semiconductor formed using III-V materials, indium and phosphorus, can therefore be "doped" to have a negative charge. The active layer (photosensitive) 2 may have a thickness of about 2 μχη to about 14 μτη. In some embodiments, additional support / plating layers may be included to provide a transition of the active layers from a lower bandgap to a higher bandgap. As a result, the epitaxial structure that grows on the substrate can be as thin as 3 to 5 μm or as thick as a few micrometers for complex structures, which may or may not include etch stop layers.
    In one embodiment, the raw slice 1 can be isolated by performing a "passivation" step which results in the deposition of an iscianre / dielectric layer 4 on the surface of the bare slice. The insulating layer can prevent degradation of the materials and limit surface conditions due to oxidation, chemical etching, exposure or contamination. The insulating / dielectric layer 4 may comprise at least one homogeneous film of silicon nitride (SiNx), of silicon oxide (SiOx), of alumina, of ALD or of natural oxides. The insulating layer 4 may be formed by plasma deposition such as PECVD, by thermal processes such as wet oxidation, by evaporation techniques such as electron beam deposition or by electrochemical processes such as anodic oxidation. The step of forming the insulating layer 4 may be called dielectric passivation or surface passivation. Dielectric passivation is intended to provide electrical isolation from surface metals and to provide a hard mask for subsequent processes such as etching, diffusion or ion implantation.
    Formation of photodiodes.
    As shown in FIG. 3B, in a method of forming a photodetector of an embodiment, such as a PIE photodiode, regions of the insulating layer (passivation film) 4 may then be etched to form diode junction windows. One window configuration can be defined using standard photolithographic methods. For example, a configured photoresist can be formed using a mask designed for the specific application. With the configuration of windows formed in the dielectric film photolithographically, a local doping such as P + type doping in the active layer 2 using a metal with fewer valence electrons than the group III atoms, especially the Zinc, beryllium or cadmium can be made to form a P + 5 region. Formation of the P + region can be achieved using thermal diffusion methods or ion implantation.
    It should be noted that a method for forming PIN photodiodes of pixels is not necessarily defined by the "planar" methods as described above. In another embodiment, a "MESA" etching process may be employed in material systems where there is no advantage in avoiding exposure of the sidewall junctions. Accordingly, the method described above can be used when higher band gap materials are employed to minimize surface leakage currents from exposing pn junctions. When a homojunction is used or for reasons of cost, performance or otherwise, an epitaxially grown junction may be desirable. In such an embodiment, the method for configuring and forming localized P + regions or pixels is replaced by the inclusion of P + layers in the epitaxial structure and, as such, the continuous P + film must be configured and etched at sufficient depth to break the electrical communication from one pixel of the P + region to another. We therefore leave "mesas" of pixels. It is also known in the art to use a common P-type semiconductor with N-type pixels located according to similar methods described in these embodiments. The current nomenclature used to describe the two polarities is "current cathode" or "current anode", where the current node designates the type of anion or cation of the global semiconductor. The pixel would then be defined by forming localized regions of the opposite type - thereby forming pn junction boundary layers around each pixel, which is the basis of the functionality of the diodes. Accordingly, this other distinct diode forming method includes the step of etching the pn junction to form mesa pixels and can be used with material systems such as HgCdTe, InSb, etc. Once the junctions of the diodes are formed between the P + 5 region and the active layer 2, the photodiode fabrication process can be terminated by subsequent etching and metallization processes using a selection of methods from photolithographic removal or recessed damasquinage to form metal contacts 6. These methods of addition or subtraction to form a metal contact 6 on semiconductor wafers are common to those skilled in the art for the formation of metal contacts P + or N + configured . For example, in one embodiment, a contact metal Pf may be selected on the basis of adhesion, a barrier and a higher metal commonly consisting of a metal or a stack of metals selected from The following ; Ti, Cr, Ni, Fd, Pt, Au, AuZn, Cu, Al, etc. On the other hand, N + contact metals can be chosen to obtain a low contact resistance or "ohmic" conditions. For example, N contacts may include, but are not limited to, AuGe, Cr, Ni, Ti, PtAu, Cu, TiW, etc.
    Finally, a buffer (interconnection) 7 made of indium, for example, may be formed on the contact metal 6 as shown in FIG. 3D. Other suitable metals may be chosen for interconnection 7. Photodiode array (PDA)
    In one embodiment, a 2D focal plane array (FPA) is formed. The FPA may comprise a two-dimensional pixel grid formed of a plurality of pixel photodetectors such as the pixel photodetector shown in FIG. 3D, formed on a shared substrate, and can be used for a wide range of image resolution and pixel pitch. If the manufacturing processes are not limited to these resolutions, in one example, an IRFPA can have a resolution of 320x240 at a resolution of 1280x1024 and a pixel pitch of 10 μη at 40 pm. Accordingly, as shown in Figs. 4A to 4E, the embodiments described herein include an array of pixel photodiode photodetectors 8 which may be integrated for use in a focal plane array. As discussed above, the photodiode array may be formed on a common wafer 1 which comprises a substrate 3, an active layer 2 and an insulating layer 4.
    Hybridization in ROIC
    Hybrid FPAs employed in IRFPA assemblies, where the photosensor is formed in a support external to that of the output circuit, can be interfaced with the output electronics in GaSb, InAs, InSb, GaAs buffer technology. The flip-chip techniques employed for image sensors commonly use indium contacts deposited or plated directly on the diode contacts 6, especially the interconnects 7 illustrated in FIG. 4A.
    As shown in FIG. 4B, corresponding buffer arrays may be deposited on the output IC chip (ROIC) 9 wafers to form corresponding electrodes for the photodiodes of the photodiode array 8. When it is joined and placed in electrical communication with the photodiode 8 photodiode array 8 as shown in FIG. 4C, the ROIC circuit 9 may be configured, therefore, as a charge capture or charge integration device, thereby converting the photocurrents produced when appropriate energy light reaches the active layer 2 of a photodiode in voltages, and multiplexes photocurrents for use in image analysis or video display.
    Interconnection technology for IRFPAs commonly uses indium for its high ductility and its ability to withstand large thermal vortices without communicating stress due to the lack of CTE agreement of detector material and ROIC silicon. However, those skilled in the art will also understand that other metal schemes or other interconnection technology may be used, for example, these other interconnections may include Cu and Cu alloys, insertion methods using various micropoints, abutments, microtubes or direct slice bond contacts.
    The composite semiconductor substrate layer 3 may have a thickness of about 500 to 650 μm and may comprise more than one layer, in particular layers of InP, GaAs, InSb, InAs, GaSb. These layers of materials can be thinned, as shown in FIG. 4D, employing an etch stop or other chemo-mechanical process or a purely mechanical bulk removal process to form a thinned blocking layer 11. The remaining material forming the thinned blocking layer 11 must be thin enough to allow formation of the appropriate vias to transmit photons at the wavelength of interest. Interconnect holes, such as blind vias 13, may be configured as a thinned blocking layer 11 to form a configured / perforated blocking layer 12 as shown in FIG. 4E.
    As discussed above, the thickness of the configured / perforated blocking layer 12 remains substantially that of the thinned blocking layer 11 so that it can transmit radiation having a first wavelength, while blocking radiation. having a second wavelength that is less than the first wavelength. The blind vias 13 may be etched to the remaining thickness of the substrate or buffer remaining after each removal of the etch stop layer, for example the thinned blocking layer 11. The blind vias 13 may be configured to have a diameter sufficient to permit a higher energy photon rate from the vias 13 from the radiation having a second wavelength, such as visible light, to pass through the vias and reach the active layer. As a result, the blind vias 13 may be formed to have a diameter that is in the order of the wavelength of visible light or more and may include a diameter of about 0.1 μm to about 1 μm. pm and a diameter of about 0.5 pm to about 1 pm. The configured / perforated layer 12 may be passivated (not shown) to minimize or eliminate defects or surface conditions in the exposed low band gap material which could contribute to detector noise. Therefore, although a small diameter of the vias allows the electrical field of the plating layer to promote adequate surface build-up, a reverse passivation method can be used.
    As shown in FIG. 5, a hybrid focal plane array 10 may comprise a photodiode array S in which its photodiodes are in electrical communication with the electrical contact of a ROIC 9. The photodiode array may comprise an In thinned and configured which forms a configured / perforated blocking layer 12 which comprises a configuration of blind vias 13. The photodiode array may also comprise an active layer of InGaAs 2. The back of the photodiode array may be exposed to a radiation source and the configured / perforated blocking layer 12 may serve as an incident surface for the incoming photon flux from radiation 22 having a first wavelength and radiation 20 having a second wavelength which is smaller than the first wavelength. In some embodiments, antireflective (AR) coatings (shown) may be formed on the configured / perforated blocking layer 12. For example, silicon nitride, PZCVD may be in the form of a monolayer AR film suitable for visible light and SWI light, in the wavelength range of about 500 nm to about 1700 nm. Those skilled in the art will recognize that other methods of forming multilayer stacks are common in the industry. Additional treatments, such as wet etchings or in situ surface treatment, may further be used to minimize surface conditions from bound oxide or other charged ions.
    In an embodiment farm using an active layer of InGaAs is a lattice or lattice fitted on an InP substrate. Without thinning the substrate, a photo response is limited to radiation having a longer wavelength of about 1.1 microns. In the meantime, the active layer which may be an arrayed InGaAs layer may be photosensitive to radiation having a wavelength of about 1.7 μm. By thinning the substrate to a thickness of about 0.5 μm to about 2 μm, a support layer can be formed with sufficient transmission to obtain a visible response in the device with radiation having a wavelength as low as about 450 nm (blue light). However, the thickness of the substrate during a thinning process must be carefully controlled, as small variations may result in dramatic changes in the low end wavelength detection range. For example, because the InP has an absorption coefficient such that it can serve as a long-pass filter, a support layer having a thickness of more than about 2 μm can result in a sufficient visible response that is cut off. in order to limit the utility for imaging in visible light. As such, not only the thickness of the nominal target is important, but also, in a realization firm not using a perforated layer such as that described in the invention, any variation in thickness of the blocking layer will have a significant impact on the uniformity of the short wavelength response.
    By perforating the thin layer of InP to form the perfected / configured carrier layer 12, for example, a photo response at a wavelength of 450 nm can be more consistently achieved. uncouple the thickness variation in the In layer of passage in photo response. In other words, by configuring the InP support layer, a desired thicker layer that provides electrical and mechanical benefits as discussed above, can be modified without degrading the performance of the device.
    For example, conventional visible-SWIR or NIRSWIR devices provide a 10-15% response at 450 nm, 30-50% up to 600 nm, increasing up to 50-80% once above of 1100 nm. Although it is not limited to a particular theory, it is believed that a device comprising the hybridized focal plane array of the forms that this embodiment described herein can boost the 450 nm response to 30 to 50% and smooth the response on the range of 600 nm to 1100 nm, thus providing improved visible response performance.
    In one example, the advantage of the improved visible response for SWIR imaging products comprising the embodiments described herein can be achieved in applications such as driver vision enhancement or in portable systems such as industrial systems or military equipment systems. For example, a stronger visible response provided by embodiments described herein may provide more intuitive imaging, which benefits SWIR without losing situational awareness from visible signals of commonly used pigments.
    If the invention has been illustrated with reference to one or more implementations, modifications and / or variants may be made according to the illustrated examples without departing from the spirit and scope of the appended claims. Further, if a particular feature of the invention may have been described with reference to only one of several embodiments, this feature may be combined with one or more other features of the other implementations as may be desired and as this may be advantageous for any given or particular function.
    For example, in some embodiments, etch stop layers may be used to ensure adequate thickness of the remaining pad / plating layer. This feature allows a robust design that is less vulnerable to defects due to pitting, fractures or other causes. Thicker plating layers made possible by the inclusion of an etch stop layer to prevent over-thinning can also improve current resistance performance for load uniformity against larger devices .
    In some embodiments, etch stop layers can not be used. Accordingly, a chemical mechanical or purely mechanical process can be used to thin the substrate to form a thinned support layer. A configured / perforated carrier layer configuration with a formed blind vias network passing therethrough provides higher etch stop thickness specifications. This can be followed by ur. careful control by dry etching techniques to form the blind holes at appropriate depth to achieve the desired result.
    In addition, some embodiments described herein are without limitation with respect to a particular pattern or configuration of the vias network. In some embodiments, the blind vias have a diameter sufficiently smaller than the pitch of the pixel grid. Accordingly, these configurations include a plurality of interconnect ports per cell unit so that the photo response is uniformly distributed and no variation in the fixed pattern response is observed. This vias distribution may be provided to ensure the alignment of a non-critical feature to achieve the desired response. In embodiments comprising planar (monolithic) structures for which the scattered or implanted junction allows a continuous volume of active area between the pixels, this characteristic will be even less critical. In realization farms comprising shallow trenched mesa pixels, for which the mesa is only deep enough to isolate individual pixels, the alignment of the intersecting holes becomes larger. -
    In the meantime, in embodiments comprising: deep trench mesa devices for which the active surface is completely eliminated between individual pixels, the via hole must be centered in the optical path for each pixel. Accordingly, to obtain the best advantage and the highest sensitivity using this approach, preferred embodiments such as those illustrated in FIGS. 2-5 include these planar (monolithic) structures that provide better use of minority carrier scattering.
    In certain embodiments, for example those including video speed imaging or a working cycle below the MHz, the experimental collection efficiency for the carriers generated between the pixels may be 100%. Accordingly, in preferred embodiments, aligning the blind vias is not critical to achieve high efficiency of the photocarriers generated by the high energy photons passing through the vias. It should be noted that on. Further advantage of such an agnostic alignment feature provides embodiments suitable for matrix level operations or wafer scale operations. This provides the opportunity for a process engineer, depending on the capacity of the process, to utilize the embodiments described herein at various stages of process maturity. In fact, the embodiments described herein may be amenable to wafer scale operations so that matrix-to-wafer binding allows post-hybridization processing, which makes photolithography and etching necessary for the formation of vias consistent with typical manufacturing operations, using the same tooling as the existing methodology. Accordingly, the blind orifices of the embodiments may be formed using known techniques such as wet etching, reactive ion etching, ICP, etc., including the use of any etching mask that is standard for the corresponding process, in particular a photoresist or other configured material. Other embodiments described herein may include blind vias having predetermined depths. In some embodiments, it is advantageous to stop the blind via at the interface between the plating (blocking) layer and the active layer as illustrated in FIG. In some embodiments, it is desirable to form vias which penetrate the active layer. It will be appreciated that deeper vias may increase the problems associated with surface recombination and charge capture. However, in embodiments in which adequate passivation of surface states is provided, higher energy photons may be delivered closer to the diode depletion zone than was previously possible in conventional devices. . Thus, for active materials such as silicon, in which the lifetime of the minority carriers is short, or in applications where load latency from one frame to another is problematic, delivery of photocarriers closer to the collection area can improve the temporal response, which enhances spatial and temporal resolution.
    Although it is not limited to a particular theory, it is believed that etching to form the plurality of vias could have an impact on the spatial distribution of the electric field. Accordingly, in embodiments, a specific configuration of the vias distribution may form a "lens" focus or directional focus for the charge, so that the carriers can be focused as determined by the spatial distribution of the vias. vias and the polarization applied to the plating layer. This can also lead to an improved MTF (modulation transfer function). In this embodiment, the alignment may be critical. As a result, slice-wide operations may be more desirable than a matrix-level configuration.
    In embodiments, wafer processing typically comprises thinning the substrate and polishing it to a sufficient extent to achieve acceptable total thickness variation (TTV) and acceptable surface roughness. In embodiments, wafer thinning operations may be performed prior to hybridization. Thin slice handling methods, such as those used in advanced 3D-C applications, can be used to pre-thin a substrate-based focal plane array removed prior to hybridization. In embodiments, complete removal of the substrate can be achieved after hybridization using individual device processing measures for these critical thinning operations. '
    In addition, some embodiments provide a specific application to composite semiconductors because of the intrinsically backlit hybrid composition. However, it is believed that the embodiments described herein may utilize backlit silicon imaging systems to provide local regions of lesser thickness when desired.
    Moreover, to the extent that the terms "including", "includes", "having", "a", "with" or variations of these terms are used in the detailed description and in the claims, these terms are meant to be inclusive in a similar way to the term "comprising". As used herein, phrase fractions such as "one or more", for example, A, B and C, mean any of the following expressions: A, B or C alone; or combinations of two, such as A and B, B and C, and A and C / or combinations of three, A, B and C. Other embodiments of the invention will be apparent to those skilled in the art by considering the specification and practice of the invention described herein. The specification and examples are intended to be considered by way of example only with a true scope and spirit of the invention which are indicated by the following claims. Legends of FIGS. 1: wafer 2: active layer 3: substrate / support layer 4: insulating / dielectric layer 5: P + 6 region: contact metal 7: interconnection 8: photodiode photodiodes with pixels 9: integrated reading circuit 10: hybridized focal plane array 11: continuous support layer 12: configured / perforated blocking layer 13: blind vias 20: second wavelength 22: first wavelength
    权利要求:
    Claims (20)
    [1]
    A focal plane array comprising: an array of photodetectors, each photodetector in electrical communication with a corresponding one of an electrode of an output integrated circuit, wherein the photodetector array comprises: an insulating layer; a blocking layer comprising at least one blind interconnection hole; and an active layer formed between the insulating layer and the blocking layer, wherein the material of the blocking layer transmits radiation having a first wavelength and reflects radiation having a second wavelength which is less than first wavelength, and wherein a diameter of the at least one blind via is chosen to allow radiation of the second wavelength to pass through the at least one blind via.
    [2]
    A focal plane array according to claim 1, wherein the material of the blocking layer transmits infrared radiation and reflects visible radiation and wherein the diameter of the at least one blind interconnection hole is selected to allow a visible radiation to pass through the at least one blind via.
    [3]
    The focal plane array of claim 1, wherein the at least one blind via comprises a network of blind vias.
    [4]
    The focal plane array of claim 1, wherein the diameter of the at least one blind via is from about 0.1 to about 1.
    [5]
    The focal plane array of claim 1, wherein the at least one blind via extends from one surface of the blocking layer to an interface of the blocking layer and the active layer.
    [6]
    The focal plane array of claim 1, wherein the at least one blind via extends from one surface of the blocking layer and enters the active layer.
    [7]
    The focal plane array of claim 1, further comprising an etch stop layer formed between the blocking layer and the active layer.
    [8]
    The focal plane array of claim 1, wherein the blocking layer comprises InP, GaAs, InSb, InAs or GaSb.
    [9]
    The focal plane array of claim 1, wherein the active layer comprises at least one layer selected from the group consisting of InP, InGaAs, InAsP or InGaAsP.
    [10]
    A method of forming a focal plane array comprising the steps of: forming a photodetector array, wherein the photodetector array comprises: an insulating layer, a blocking layer comprising a material that transmits radiation having a first wavelength and reflects radiation having a second wavelength that is less than the first wavelength, and an active layer formed between the insulating layer and the blocking layer; electrically bonding the photodetector array to an output IC, wherein each of the photodetectors is placed in electrical communication with a corresponding one of an electrode of the output IC; and forming at least one blind via in the blocking layer of the photodetector array, wherein a diameter of the at least one blind via is selected to allow the radiation of the second wavelength to pass through the at least one blind interconnection hole.
    [11]
    The method of claim 10, wherein forming the at least one blind via hole includes etching the blocking layer.
    [12]
    The method of claim 11, further comprising forming the active layer on a substrate and thinning said substrate to form the blocking layer.
    [13]
    The method of claim 10, wherein the material of the blocking layer transmits infrared radiation and reflects visible radiation and wherein the diameter of the at least one blind interconnection hole is selected to allow the passage of radiation. visible through the at least one blind via. .
    [14]
    The method of claim 10, wherein the at least one blind via comprises a network of blind vias.
    [15]
    The method of claim 10, wherein the diameter of the at least one blind via is about 0.1 μm to about 1 μηα.
    [16]
    The method of claim 10, wherein the at least one blind via extends from one surface of the blocking layer to an interface of the blocking layer and the active layer.
    [17]
    The method of claim 10, wherein the at least one blind via extends from one surface of the blocking layer and enters the active layer.
    [18]
    The method of claim 10, further comprising an etch stop layer formed between the blocking layer and the active layer.
    [19]
    The method of claim 10, wherein the blocking layer comprises InP, GaAs, InSb, InAs or GaSb, and wherein the active layer comprises at least one layer selected from group consisting of InP, InGaAs, InAsP or InGaAsP.
    [20]
    A photodetector, comprising: a blocking layer comprising at least one blind interconnection hole; and an active layer formed between the insulating layer and the blocking layer, wherein the material of the blocking layer transmits radiation having a first wavelength and reflects radiation having a second wavelength which is less than first wavelength, and wherein a diameter of the at least one blind via is chosen to allow radiation of the second wavelength to pass through the at least one blind via.
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    同族专利:
    公开号 | 公开日
    IL232730D0|2014-08-31|
    TW201505162A|2015-02-01|
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    TWI615953B|2018-02-21|
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    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US5656848A|1995-03-29|1997-08-12|Texas Instruments Incorporated|High thermal resistance backfill material for hybrid UFPA's|
    US5973316A|1997-07-08|1999-10-26|Nec Research Institute, Inc.|Sub-wavelength aperture arrays with enhanced light transmission|
    US20070170359A1|2006-01-26|2007-07-26|Syllaios Athanasios J|Systems and methods for integrating focal plane arrays|
    US20090045395A1|2007-08-17|2009-02-19|Kim Jin K|Strained-Layer Superlattice Focal Plane Array Having a Planar Structure|
    US5876880A|1995-05-30|1999-03-02|Ims Ionen Mikrofabrikations Systeme Gellschaft M.B.H.|Process for producing a structured mask|
    US6236033B1|1998-12-09|2001-05-22|Nec Research Institute, Inc.|Enhanced optical transmission apparatus utilizing metal films having apertures and periodic surface topography|
    US8299497B1|2010-06-30|2012-10-30|Sandia Corporation|Near-infrared photodetector with reduced dark current|US9508681B2|2014-12-22|2016-11-29|Google Inc.|Stacked semiconductor chip RGBZ sensor|
    US9842868B2|2015-10-26|2017-12-12|Sensors Unlimited, Inc.|Quantum efficiencyrestricted infrared focal plane arrays|
    WO2019146299A1|2018-01-23|2019-08-01|ソニーセミコンダクタソリューションズ株式会社|Imaging device|
    US10727267B2|2018-09-12|2020-07-28|Sensors Unlimited, Inc.|Interconnect bump structures for photo detectors|
    法律状态:
    优先权:
    申请号 | 申请日 | 专利标题
    US13/986660|2013-05-22|
    US13/986,660|US9111830B1|2013-05-22|2013-05-22|Perforated blocking layer for enhanced broad band response in a focal plane array|
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